About: C-slowing

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Digital circuit design technique

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dbo:description	digital circuit design technique (en)
dbo:wikiPageExternalLink	http://brass.cs.berkeley.edu/documents/cslowfpga.ppt http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/fpga03/pdffiles/7_2.pdf http://www.ee.washington.edu/faculty/hauck/publications/PipeRouteTCAD.pdf http://www.ee.washington.edu/faculty/hauck/publications/RapidArchExploreJ.pdf https://web.archive.org/web/20060517015646/http:/www.cs.berkeley.edu/~yatish/cs252/252report.pdf https://web.archive.org/web/20060721183224/http:/halcyon.usc.edu/~zbaker/zbakerFPGA.pdf
dbo:wikiPageWikiLink	dbr:Barrel_processor dbc:Gate_arrays dbr:Latency_(engineering) dbr:Pipeline_(computing) dbr:Hardware_register dbr:Field-programmable_gate_array dbr:Retiming dbr:Throughput dbr:Digital_circuit dbr:Clock_cycle
dbp:title	2.400000 (xsd:double)
dbp:url	http://web.archive.org/web/20240612021916/https:/www.intel.com/content/www/us/en/docs/programmable/683353/23-4/time-domain-multiplexing.html
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dct:subject	dbc:Gate_arrays
gold:hypernym	dbr:Technique
rdfs:label	C-slowing (en)
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